RTL, often referred to as Register Transfer Level or Register Transfer Language, is a high level method to model digital circuits. RTL eliminates the need to define a logic circuit at the gate level or the transistor level. This is important. Today’s electronics system contain tens of billions of logic gate equivalents. It would be an impossible task to manually design a system from simple gate constructs. Instead, in RTL one uses logic blocks, that represent hundreds or thousands or millions of gates, to build large scale ASIC chips. Some RTL building blocks, like an Arithmetic Logic Unit (ALU), are relatively small, in the order of 400 logic gate equivalents. On the other hand, Digital Signal Processing blocks, which can consist of thousands of ALUs, are relatively large, 400,000 logic gate equivalents as a rough estimate.
When an ASIC chip designer sets out to design a System on a Chip (SOC), to state it simplistically, the designer first decides on the building blocks that will be used in the design, chosen from a prebuilt library. The designer then connects these building blocks together, with virtual wires and buses. to form the system. Electronic simulations are then performed to test and verify that the electronic system will work as intended.
These simulations are based on prebuilt gate or even transistor level models that the larger RTL blocks are mapped too. In the case of RTL syntheses, the RTL blocks may not be mapped to an existing gate model. Instead, the gate level models are synthesized from the overall high level construct that the RTL block implies. For example, if the designer was using an ALU in the design, the designer would place an RTL level ALU block in the design. Then, the designer would invoke an ALU synthesis tool, assign electrical specification and cost constraints to the ALU, like power, critical timing path delays, even noise specifications and silicon area constraints, and then invoke the ALU synthesis tool. The ALU synthesizer would then generate the gate equivalent model that would be used in the simulation, a simulation that would effectively model the performance of the chip after it was manufactured.
The SOCMatrix, or System on a Chip Matrix, a poster, was designed for those that must understand the chip design process, a process that includes RTL and RTL design tools. Professors, both high school and college students as well as practicing electronic engineers will find the poster useful for not only teaching and training, but also as a handy reference. Chip design is a complex process, that the SOCMatrix poster organizes and simplifies.
