Learn Your AI Modeling ABCs …….. Behavioral Modeling in LTSPICE …Mark Stansberry …..
Contact: mark@statisticsmatrix.com
Behavioral modeling departs from the traditional SPICE transistor level modeling that is used for circuit simulation. Behavioral models, available within most free and high-end Electronic Design Automation software, can be used to replicate the functionality of analog, digital and mixed signal circuits without the nuances and complications that detailed passive and active SPICE, Verilog and C++ circuit models present. Another way to put it is that behavioral models can be used to create idealized circuit behavior. As such is the case, a further extension of that idea is that behavioral models can be used to create ideal models of neural processes that are used to mimic human intelligence, i.e. artificial intelligence.
The LTSPICE behavioral model and simulation below, represents an idealized, DC biased model of a JFET (Junction Field Effect Transistor) based amplifier, a model which can also be used to represent an idealized neural model. More generally, within certain limitations that can be overcome, the model can be used as a generic JFET model that can be tailored to meet the specifications of a wide variety of JFETs from different chip manufacturers.
Typically, if one increases the drain resistor, the AC output voltage (VO), will have higher AC peak voltage gain for a specific JFET IV curve family One should note here that a JFET is a voltage controlled dependent current source. That is when the input voltage is fixed to a specific range, the drain to source current will vary between a specific current range. Because of this increasing RD, the drain resistance, will increase the voltage gain. Keep in mind that the dependent current source will only sink current and not source it.
With this JFET behavioral model, one can define a different JFET that has a unique transconductance and threshold voltage by just changing the DC IV midpoint bias behavioral parameters (not shown). That is because the model assumes that the midpoint bias is always centered at the midpoint of the family of the JFETs IV curves. A different midpoint bias automatically assumes a different JFET with a different IV curve family. The DC bias component at VO most always needs to be removed from the AC output voltage. This is done with the DC blocking high pass filter shown (which is set to have a cut-off frequency much higher than the frequency of the input signal).
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