Register Transfer Language (RTL) is a much quicker way to put together a model of a digital electronics system than using gate and flip-flop level models. With RTL one can define a combinatorial and sequential logic circuit that consists of hundreds of equivalent logic gates and flip-flops in seconds as compared to several minutes or hours for a gate and flip-flop based netlist or schematic capture implementation. This is an important consideration since today’s electronic systems are in the order of a trillion gate equivalents.
On the other hand, if your electronic design automation system has digital libraries that have many pre-built and high density gate level models, it is less of an issue. However, still RTL’s power is customization and electronic structure duplicity. For example, one can create a shift register of any length, 10-bits, 15-bits or more, with just a few lines of RTL code. By comparison one might have to string together several shift register gate level models to accomplish the same thing. Here, RTL holds the design time advantage when wants to create an arbitrary n-bit shift register. However, still, one must in the end synthesize the RTL coded logic design to a gate level vendor specific netlist, ASIC vendor library conversion compatibility is an issue. This does take computer time, not human time, and in some cases can lead to errors in the conversion, but not that often. The process of converting from an RTL coded digital electronics design to a gate level working design is called synthesis, or more precisely RTL to Gate Level Synthesis.
Contributors: Mark Stansberry at the IPCoreMatrix at Redbubble.
